1. Field of the Invention
The present invention relates generally to field effect transistors (FETs) and to the preparation of integrated circuits containing a plurality of the FETs. More particularly the present invention is related to a novel FET having a gate electrode which, wherever desired, makes a self-registering or misregistration tolerant electrical connection to a metallic high-electrical conductivity interconnection line. Furthermore, the present invention provides FETs which have a thick chemically vapor deposited insulation over the diffused source and drain regions, over gate electrode regions, and over the field isolation regions to significantly reduce the coupling capacitance between the interconnection line and the insulated regions.
2. Description of the Prior Art
It is well known in the prior art that the FET is an important electrical switching and amplifying device used in large scale integrated circuits. Such integrated circuits can contain tens or even hundreds of thousands of FETs on a single semiconductor chip which measures about one quarter of one inch on a side. The area devoted to each FET and the ease of electrically interconnecting a plurality of FETs are important factors in determining the device packing density on the chip. The electrical time constants of the integrated circuit are in part determined by the switching speed of the transistor, and by the resistance-times-capacitance (RC) time constant of the interconnection lines. Consequently, reduction of the capacitance between the interconnection line and the semiconductive substrate is an important requirement in integrated circuits.
Furthermore, in integrated circuits, electrical interconnection lines must frequently cross over or under other electrical signal lines and be insulated from them. The capacitance between such lines undesirably cross couples signals from one line to another and thereby increases the electrical noise on the signal lines. Consequently, reduction of the coupling capacitance between interconnection lines and other signal lines is an important requirement in integrated circuits.
The method employed to fabricate the integrated circuit determines both the area of the device and the electrical properties, i.e., the resistance and the capacitance, of the interconnection lines. Therefore, it is desirable to simultaneously reduce both the device size and the interconnection line capacitance. The material employed for the gate electrode of the FET influences the properties of the FET and the procedure for fabricating the FET. The most common gate materials used in the prior art are aluminum (a low-melting temperature metal), polysilicon (i.e. polycrystalline silicon -- a high-melting temperature nonmetal), and tungsten and molybdenum (high melting temperature metals). The present invention relates generally to FETs wherein the gate electrode material is a high temperature material such as polysilicon or tungsten and wherein the gate material can be covered with a chemically vapor deposited insulator without seriously degrading the properties of the gate material.
With high melting temperature gate materials, it is relatively easy to fabricate doped silicon source and drain regions self-aligned with respect to the edges of the gate electrode. In the self-aligned gate technique, which is known in the art, the gate electrode is delineated prior to forming the source and drain regions. Consequently, the edges of the gate material determine the boundaries of the diffused or ion implanted source and drain regions. For example, a method of fabrication for ion implanted source and drain regions self-aligned to a polysilicon gate is described in "Design of Ion-Implanted MOSFET's with Very Small Physical Dimensions" by R. H. Dennard et al., IEEE J. Solid-State Circuits, Vol. SC-9, pp. 256-268, October 1974.
Of the various high melting temperature gate materials described hereinabove, polysilicon is by far the most popular for commercially fabricated integrated circuits for several reasons. Polysilicon can withstand high processing temperatures without degradation while other high melting temperature materials such as the metals tungsten and molybdenum tend to become unstable during exposure to high processing temperatures, particularly in the presence of oxygen. Furthermore, polysilicon offers potentially higher gate oxide reliability than other gate materials.
Yet another attractive feature of polysilicon is that it may serve not only as a gate electrode material, but as an interconnection line material as well. Thus an integrated circuit may be constructed of polysilicon gate FETs and interconnection lines of doped silicon, doped polysilicon, and/or metal. In terms of sheet resistance, at best silicon and polysilicon lines are degenerately doped and at the best have sheet resistances many orders of magnitude higher than that of metals such as aluminum. Doped silicon and doped polysilicon lines have about the same sheet resistances, but doped silicon lines generally have higher sheet capacitance because they are imbedded in the silicon substrate rather than electrically insulated from it by the field oxide isolation layer. Metal lines are also insulated from the semiconductive substrate by the field isolation layer. Consequently, doped silicon lines offer the largest, polysilicon lines smaller, and metal lines favorably much smaller RC time constants. Thus, it is generally desirable to construct an integrated circuit array of metal and polysilicon interconnection lines whenever possible. At intersection points these lines may either cross over each other, or be electrically connected together.
As discussed hereinabove, polysilicon may be used to provide gate electrode, interconnection line patterns, or both. One of the most vexing problems associated with the polysilicon gate FET technology is the means for providing electrical connection between the polysilicon material and the high-electrical conductivity, metallic, interconnection line material. In the prior art, a common means for providing electrical connection has been to photolithographically delineate and then define by etching a small hole or via through the insulator over the gate material. Because of diffraction effects, this hole cannot be made equal in diameter to the minimum exposable lithographic linewidth, but must be larger. Furthermore, because of mask to mask misregistration inherent in any lithographic exposure system, the area of the gate material beneath the via and the area of the interconnection material above the via must be enlarged to provide a tolerance for misregistration and for area modification due to etching and possible overexposure of the photoresist material. The result of all of the above considerations is that the area devoted to the polysilicon contact is relatively very large, in fact, it may even be significantly larger than the area of the channel region of the FET itself.
No prior art methods of providing a self-registering or misregistration tolerant electrical connection between the gate electrode and the metallic interconnection line are discussed by Kalter et al in IBM Technical Disclosure Bulletin, Vol. 14, No. 10, p. 3176, March 1972, and by Rideout in IBM Technical Disclosure Bulletin, Vol. 17, No. 9, p. 2802, February 1975. In these prior art methods, the insulation over the source and drain regions is provided by thermal oxidation of the semiconductor substrate, a portion of the substrate material being converted to an insulating oxide. Oxidation over the polysilicon gate is prevented by an oxidation barrier and gate masking layer. When the oxidation barrier layer is removed, the entire gate area is revealed for contacting. A metal interconnection line such as aluminum that crosses the revealed polysilicon gate will provide an electrical connection to that gate. Because the entire polysilicon area is revealed, the metal line and the polysilicon areas advantageously do not need to be precisely registered with respect to each other in order to make electrical connection. Much more precise registration is required, however, when the metal line must contact the polysilicon gate via a conventional contact hole etched through an oxide layer that exists over the gate.
Two restrictions apply to the oxidation barrier method for fabricating self-registered gate contacts as described by Kalter et al and by Rideout. First, the thickness of the thermally grown oxide is limited by the amount of substrate material that allowably can be converted to oxide, and by the allowable high temperature treatment time during which doped silicon regions such as source and drain regions, channel regions, and doped channel-stopper field regions diffuse and expand. Second, since the entire polysilicon area is revealed for contacting, wherever a metal line and a polysilicon region cross they will make electrical connection. Thus, it will not be possible to use the polysilicon as an additional level of interconnection without resorting to the use of at least one additional photolithographic masking step.
The present invention does involve an additional photolithographic masking step but is distinct in that rather than using only thermally grown oxide insulation, an etching stopping layer is included which allows the use of a thick deposited oxide insulation layer which provides much lower processing temperatures and relatively thicker insulation layers. Another distinction of the present invention over the prior art is that the FETs fabricated by the present method may be interconnected to form an integrated circuit wherein the metallic interconnection lines have relatively low capacitive coupling to the doped silicon regions, polysilicon lines, and substrate regions over which they cross without making electrical connection due to the presence of the relatively thicker, deposited oxide, isolation layer. Yet another distinction of the present invention is that the polysilicon gate electrode material may be used as an interconnection line material and may cross under metallic interconnection lines without making electrical connection to them, wherever desired.